At present, due to development of semiconductor integrated circuits, it is common to process an analog signal detected from a sensor element, etc., as a digital signal in a signal processing unit within a semiconductor device. Thus, an analog-digital converter (hereinafter, also referred to as AD converter) for converting an analog signal into a digital signal is an absolutely indispensable element used in many semiconductor devices and there is a case where the performance of the AD converter determines the performance of the entire system mounted on the semiconductor device. Thus, it is necessary to improve the performance of the AD converter mounted on the semiconductor device, such as a microcomputer and system LSI, and there are a variety of techniques known for improving the performance of the AD converter. For example, by adopting the cyclic type AD converter described in Patent Document 1, it is possible to reduce the size and by adopting the pipeline type AD converter described in Patent Document 2, it is possible to increase the processing speed.
FIG. 16A is a diagram illustrating a digital approximator 101 having a 1-bit configuration used as a basic circuit in the conventional cyclic-type analog-digital converter and pipeline-type analog-digital converter. The digital approximator 101 includes a sample holder 102 configured to sample and hold an input signal Vin and to generate a sampling signal Vs, a comparator 103 configured to compare the sampling signal Vs and a threshold value Vth and to output a digital value Qout indicative of the comparison result, and a multiplying digital-analog converter (hereinafter, also referred to as MDAC) 104 configured to amplify the sampling signal Vs by a factor of 2 and at the same time, to perform a calculation in accordance with the comparison result of the comparator 103 to generate a residual signal Vres. In the case of AD conversion with unipolar code, the threshold value Vth is half the value of a full-scale signal VFS of the input signal Vin. On the other hand, in the case of AD conversion with bipolar code, the threshold value Vth corresponds to the voltage of direct-current (hereinafter, also referred to as DC) difference 0 V. The comparator 103 is configured to output 1 in the case where the sampling signal Vs is larger than the threshold value Vth and to output 0 in the case where the sampling signal Vs is smaller than the threshold value Vth. The MDAC 104 performs a calculation to amplify the value of a difference between the sampling signal Vs and the threshold value Vth by a factor of 2 in the case where the sampling signal Vs is larger than the threshold value Vth. On the other hand, in the case where the sampling signal Vs is smaller than the threshold value Vth, the MDAC 104 performs a calculation to amplify the sampling signal Vs by a factor of 2.
FIG. 16B is a diagram illustrating an example of the input/output characteristic of the digital approximator 101. In FIG. 16B, the horizontal axis represents the input signal Vin and the vertical axis represents the residual signal Vres. The VFS is the full-scale value of the input signal Vin and the residual signal Vres, and the threshold value Vth is a value half the full-scale value VFS. The input signal Vin is amplified by a factor of 2 in the MDAC 104, and therefore the slope of a straight line indicating the input/output characteristic of the digital approximator 101 is 2. Further, when the input signal Vin becomes larger than the threshold value Vth, the MDAC 104 amplifies the value of a difference between the input signal Vin and the threshold value Vth by a factor of 2. Thus, the input/output characteristics have the linear characteristic between 0 of the input signal Vin and the threshold value Vth, and between the threshold value Vth and the full-scale value VFS, respectively, and have the characteristics that the same characteristics are repeated between 0 of the input signal Vin and the threshold value Vth, and between the threshold value Vth and the full-scale value VFS.
FIG. 17A is a diagram illustrating a cyclic type AD converter 110 including the digital approximator 101. The cyclic type AD converter 110 has a multiplexer 111 configured to selectively output an analog input signal Vana and the residual signal Vres based on a selection signal S, the digital approximator 101 configured to receive an output signal of the multiplexer 111, and a register 112 configure to sequentially store the digital value Qout output from the comparator 103 and to output the value Qout as a digital signal Dout. The multiplexer 111 is configured to form a feedback circuit by selecting the analog input signal Vana only when the digital approximator 101 calculates the most significant bit (hereinafter, also referred to as MSB) and by selecting an output signal of the digital approximator 101 when the digital approximator 101 calculates bits other than the MSB.
With reference to FIG. 16C, the sequence of the operation of the cyclic type AD converter 110 is explained. FIG. 16C is a diagram illustrating an example of a sequence to generate a 5-bit digital signal using the cyclic type AD converter 110. A bar B101 indicates the input signal Vin input from the outside of the cyclic type AD converter 110 via the multiplexer 111. In this example, the input signal Vin is larger than the threshold value Vth, and therefore the comparator 103 of the digital approximator 101 outputs 1 as the digital value Qout. The MDAC 104 of the digital approximator 101 generates the residual signal Vres by performing a calculation to amplify the value of a difference between the input signal Vin and the threshold value Vth by a factor of 2 in accordance with the comparison result of the comparator 103.
Next, the residual signal Vres generated in the MDAC 104 is fed back to the input of the digital approximator 101 via the multiplexer 111. A bar B102 indicates the residual signal Vres that is fed back to the input of the digital approximator 101 via the multiplexer 111. The signal of the second bit indicated by the bar B102 is smaller than the threshold value Vth, and therefore the comparator 103 of the digital approximator 101 outputs 0 as the digital value Qout. The MDAC 104 of the digital approximator 101 generates the residual signal Vres by performing a calculation to amplify the input signal Vin by a factor of 2 in accordance with the comparison result of the comparator 103. A bar B103 is a feedback signal of the residual signal Vres of the second bit and corresponds to the input signal Vin of the third bit. Hereinafter, in the similar manner, the comparator 103 generates a digital signal and at the same time, the MDAC 104 generates the residual signal Vres used as the input signal Vin of the next stage in accordance with the comparison result of the comparator 103. As a result, in the example illustrated in FIG. 16C, the digital signal Dout of (10101) is obtained.
FIG. 16D is a diagram illustrating a sequence in the case where the input signal Vin the same as that in FIG. 16C is input to the cyclic type AD converter 110 in which the signal amplification degree of the MDAC 104 is 2.1, not 2.0. Despite that the input signal Vin the same as that in FIG. 16C is input, in FIG. 16D, the lower-order two bits corresponding to bars B204 and B205 having slashes are converted erroneously and a digital signal (10110) is generated. This erroneous conversion results from the fact that the signal amplification degree is 2.1, not 2.0 and is caused by the erroneous calculation of the digital approximator 101.
Further, in the digital approximator 101, there is a possibility that erroneous conversion occurs also in the case where there is an offset in an operational amplifier used for signal amplification or in the case where there is a deviation in the threshold voltage Vth. FIGS. 18A to 18F illustrate examples of the AD conversion error. FIGS. 18A and 18B illustrate examples of occurrence of miscoding due to a deviation in the threshold voltage Vth. As illustrated in FIG. 18A, the Vth becomes larger than the half of the full-scale value VFS and the residual signal Vres exceeds the full-scale value VFS, and therefore miscoding as illustrated in FIG. 18B occurs.
FIGS. 18C and 18D illustrate examples of occurrence of a conversion error due to a gain error in the case where the amplification degree of the MDAC 104 exceeds 2. As illustrated in FIG. 18C, when the input signal Vin is in the vicinity of the threshold value Vth, the residual signal Vres exceeds the full-scale value VFS. Thus, such a conversion error as illustrated in FIG. 18D occurs. Further, FIGS. 18E and 18F illustrate examples of occurrence of miscoding due to a gain error in the case where the amplification degree of the MDCA 104 is less than 2.
As described above, in the conventional cyclic type AD converter 110, it is possible that a conversion error may occur in the case where the amplification degree of the MDCA 104 is not exactly 2, in the case where there is a deviation in the threshold voltage Vth, and in the case where there is an offset in the operational amplifier. Thus, it is necessary to set the amplification degree of the MDCA 104 exactly to 2, to set the Vth to the VFS/2, and to set the offset of the operational amplifier substantially to zero.
FIG. 17B is a diagram illustrating a pipeline type AD converter 120. The pipeline type AD converter 120 includes a plurality of digital approximators 101 connected in series to the input unit to which the analog input signal Vana is input. While the cyclic type AD converter 110 illustrated in FIG. 17A generates a digital signal by successive approximation by configuring a feedback circuit by one digital approximator 101, the pipeline type AD converter 120 uses the residual signal Vres generated by the digital approximator 101 in the previous stage as the input signal Vin of the digital approximator 101 in the subsequent stage, which is the difference between both the AD converters. However, the sequence to generate the digital signal Dout from the analog input signal Vana using the pipeline type AD converter 120 is the same as that of the cyclic type AD converter 110 as illustrated in FIG. 16C. Thus, in the pipeline type AD converter 120 also, as in the cyclic type AD converter 110, it is necessary to set the amplification degree of the MDCA 104 exactly to 2, to set the Vth to the VFS/2, and to set the offset of the operational amplifier substantially to zero.
As illustrated in Non-patent Document 1 and Patent Document 3, the β conversion type AD converter and the β conversion type DA converter that have focused attention on the relationship between the Markov chain and the β conversion are known. The β conversion type AD converter and the β conversion type DA converter are converters that have a high accuracy and which cover the unstableness of the circuit element by utilizing the β extension.
The β conversion type AD converter is explained simply below. The AD converter 110 described in Patent Documents 1 and 2 utilizes the fact that the relationship between a binary code bi obtained by N-step (N-bit) AD conversion for the input signal Vin with the full-scale value being taken to be VFS and the AD conversion value is expressed by expression (1).
                                          V            in                                V            FS                          =                              ∑                          i              =              1                        N                    ⁢                                          ⁢                                    b              i                        ⁢                          2                              -                i                                                                        (        1        )            
In contrast to this, the β conversion type AD converter utilizes the β extension expressed by expression (2).
                                          V            in                                V            FS                          =                              (                          β              -              1                        )                    ⁢                                    ∑                              i                =                1                            ∞                        ⁢                                                  ⁢                                          b                i                            ⁢                              β                                  -                  i                                                                                        (        2        )            
In the expression (2), the value of β is a number larger than 1 and smaller than 2. In other words, the β conversion type AD converter is not a converter that encodes a digital signal by binary coding (hereinafter, also referred to as a binary digital signal) as described in Patent Documents 1 and 2 but a converter that encodes a digital signal by β-adic coding (hereinafter, also referred to as a β-adic digital signal) using the value of β, which is a number larger than 1 but smaller than 2.
In the β conversion type AD converter also, there is a possibility that miscoding occurs in the case where the value of the amplification degree of β deviates and the amplification degree exceeds 2, or in the case where there is a deviation in the threshold voltage Vth, or in the case where there is an offset in the operational amplifier. Thus, also in the case where the β conversion type AD converter is used, it is necessary to select the value of β so that the residual signal multiplied by β does not exceed the input range of ±Vref regardless of the variations in the semiconductor manufacturing or the change in the use environment. Further, unless conversion into a binary number is carried out using an accurate value of the amplification degree of β, an error occurs, and therefore it is necessary to know the value of the amplification degree of β with a high accuracy.
As another method for reducing the influence of an offset, a digital approximator having a 1.5-bit configuration that uses the two comparators 103 is adopted. FIG. 19 is a diagram illustrating an example of the input/output characteristics of the digital approximator having a 1.5-bit configuration. In the case where the digital approximator having a 1.5-bit configuration is adopted, it is not necessary to switch the input signals in the vicinity of the full-scale value VFS and it is possible to reduce the influence of the deviation in the threshold value Vth and the offset.